With reference to FIG. 1, a conventional BGA semiconductor chip package includes a substrate 1 having a metallic pattern 3 provided therein. A chip 5 is bondingly mounted by an adhesive 4 onto the substrate 1. Chip pads (not shown) formed on the chip 5 are electrically connected by metallic wires 7 to the metallic pattern 3. A certain portion of the substrate surface including the chip 5 and the metallic wires 7 is covered by epoxy molding compound 6. A plurality of conductive pads 2 are formed on the lower surface of the substrate 1. Solder balls 8 are each formed by a reflow process on a corresponding one of the conductive pads 2. The conventional BGA package is then mounted on a printed circuit board (not shown) using solder balls 8.
The conventional BGA package, however, has a couple of disadvantages. Since the solder balls 8 of the package are positioned on the opposite surface to an active surface or a lower surface of the chip, the electrical path in the package becomes lengthy by the elongation ranging from the chip 5 through the wires 7 up to the PCB, whereby a longer access time in the package has been experienced. Further, there are limitations to the reduction of the package size.
Additionally, there is an embodiment (not shown) in which solder balls are laid out on an active surface of a package chip, however, due to requiring a tab bonding to be applied thereto for interconnection, problems of low productivity along with the difficulty of the fabrication process have yet to be solved.